Custom silicon for the economics of AI inference.
Organizations want capable AI running on hardware they control, starting with coding agents that work on source code which cannot leave the building. The cost of every AI answer is set by how fast a chip can move a model's weights, not by how much arithmetic it can do. VECTRA is an architecture built around that fact. It already runs a 27-billion-parameter model end to end on FPGA hardware, bit-exact against its reference. We are raising to build the team and take it to silicon.
parameters, all 64 layers on our accelerator
output mismatches against the quantized reference
ms per token, two hardware builds apart
unit cost at 10,000 units, against a $7,000 to $10,000 GPU card
Every question a semiconductor investor asks, answered plainly.
The FPGA prototype answers the first question. The rest is what the next financing is for.
Technical feasibility
demonstratedA 27B hybrid model runs end to end on our FPGA architecture, bit-exact, at 241 ms of hardware time per token. Live answers are served from the hardware.
Competitive advantage
partly shownMeasured: 93.9% of peak memory bandwidth in our streaming kernel, and a fused recurrence instruction that cut the hybrid-model path by 2.8×. The cost and power advantage over GPUs is projected, not measured.Our measured GPU baseline is an NVIDIA L40S: 40 tokens/s at 228 W. Flagship data-center GPUs are far faster; they are built to serve many users at once.
Economics
modelledDocumented ASIC model: $400 to $500 unit cost at 10,000 units, 15 to 30 W, 20 to 30 tokens/s per user on a 384-bit LPDDR5X board, and about 1.0 J per token against 5.7 J measured on the L40S. Assumptions are on the engineering page.
Market demand
openFirst application: private coding agents for teams whose source code cannot leave the building, alongside air-gapped and regulated sites in defense, aerospace and finance. The design-partner program opened this month. We have no customer commitments yet, and we say so.
Business model
plannedChips and modules sold to system builders first; architecture licensing for data-center partners later. To be validated with design partners.
Team
founder plus planFounder-built architecture and full stack. Hiring plan: an ASIC physical-design lead and a verification lead first, backend through a design-services partner.
Capital to first silicon
estimated$8 to $15 M at 12 nm with a design-services partner. A core-tile shuttle that proves the processor in silicon is estimated at €110 to 150k.
Next milestones
in progressA faster FPGA image with longer context for agent workloads, the silicon team, the core tile and the first design partners. Detailed below.
A different design point from the incumbents.
A model is trained once and then read from memory once for every word it produces, for as long as it is deployed. As models move into products and onto premises, the cost per answer becomes the cost that matters.
Inference is the recurring cost
Every deployed model pays the memory read on every word, every day.
Nobody builds for one user, one large model
Data-center GPUs serve many users at once and are priced accordingly. A private 27B model needs bandwidth, not a large compute array.
A verified design, running today
Streaming architecture, exact 4-bit numerics and native hybrid-model support, verified on hardware.
Every build logged
A public, dated engineering log of every build, failure and measurement.
What we have already done.
All in October 2026, on AWS F2 FPGA hardware running our own RTL.
- Oct 2026
Streaming kernel at 93.9% of peak HBM bandwidth
432.7 GB/s across 32 memory channels, with the matrix-engine array keeping up.
- Oct 2026
First bit-exact token of a 27B model on FPGA hardware
All 64 layers on the accelerator, every hidden state and output matching the reference. 533 ms of hardware time.
- Oct 2026
Fused recurrence instruction: 533 ms to 313 ms
A new vector-unit instruction for the recurrent layers, closed timing at 250 MHz and verified bit-exact on hardware.
- Oct 2026
Weights kept next to their engines: 313 ms to 241 ms
Each engine now reads its weights from the HBM channels beside it instead of across the memory switch. Verified bit-exact on hardware.
- Oct 2026
Live answers from the hardware on our public site
Questions typed on the website are answered by the model running on the FPGA, streamed word by word.
- Oct 2026
A ranked plan for the next image
A calibrated cost model of every instruction, checked against the hardware to within 1%, ranks the changes for the next FPGA image.
From prototype to product.
Process node, shuttle and tapeout timing are recommendations from our studies, not commitments. They are set with the team and partners the next financing brings in.
Prototype performance
Faster responses and longer context on the FPGA, measured against real agent workloads.
Team and partners
The first silicon hires, a design-services partner and the first design partners.
Core in silicon
A core tile on a multi-project shuttle proves clock, power and function in about 6 months.
First chip
The full chip with LPDDR5X memory interfaces, at 12 to 16 nm per our study.
Boards shipping
Boards in design partners' systems.
What the next financing accomplishes.
Round size, structure and use of proceeds are shared in conversation.
It funds
- The silicon team: physical design and verification leads, then firmware and systems.
- The core-tile shuttle: the processor proven in silicon.
- The FPGA performance program and the first design-partner boards.
- Readiness for first silicon: memory-interface IP, a design-services contract and the full-chip plan.
First silicon, estimated
- $8 to 15 Mtotal at 12 nm with a design-services partner estimated
- $2 to 8 Mmemory-interface and PCIe IP
- $3 to 6 Mphysical design, DFT and signoff services
- $1.5 to 5 Mmasks and first wafers
- From our ASIC feasibility study, October 2026. Quotes are needed before any of these become a budget.
Talk to the founder.
We can walk through the hardware, the build log, the cost model and the plan to silicon.