VECTRA · AI silicon for hardware you own
Capable AI on hardware you own.
Defense systems, robots and field equipment need a capable model on board, often with no network and a tight power budget. VECTRA is a programmable chip that runs the most capable model that fits a 16 W budget, today a 27B-class model, beside the computer a system already has. Three model families already run on our prototype, bit for bit against the reference.
measured3model families on one FPGA image
measured27Bmodel answering live on our hardware
measured0output mismatches vs reference
projected16 Wchip target for a 27B model
The working prototype
Not a render. A large model answering from our hardware.
Ask the FPGA prototype a question: a live session starts in about a minute, or replay a recorded run now.
Checking whether a session is running.
A functional prototype, not the product. It reads your question first, then writes about 5.5 tokens per second in this chat (about 150 to 180 ms of FPGA time per token, plus network). Answers stop after 96 tokens.
Recorded sessionmeasured
0.0 sone real question, timed on the FPGA
reading
writing
0 s
FPGA timehost and networkprompt token read
FPGA time per token
- prompt
- 0
- reading
- 0 s
- tokens
- 0
- FPGA / token
- 0 ms
- host / token
- 0 ms
- total
- 0 s
Real questions answered by the FPGA, replayed at the speed they ran.
The problem
Moving model weights is the bottleneck.
A data-center GPU costs $7,000 to $10,000 and draws about 230 W. A robot or a vehicle cannot carry that, and it often needs more than one agent.
13.5GB
Read from memory for every single word a model produces.
13.54 GB of 4-bit weights per token, measured from our packed model. The arithmetic is cheap; moving those bytes sets the cost, the power and the speed. One read of the model can serve several agents at once.
layer 1one tokenlayer 64 → next word
First
Defense unmanned systems
Army, SOCOM and their integrators: ground robots and drones that need a capable model on board, with no network and a tight power budget.
Then
Commercial robots and vehicles
Several agents on one module, at volume.
Later
Secure government data centers
The same programmable core on faster memory.
How VECTRA is different
Built around memory, not math.
Open models keep changing, so the chip is programmable. Select one to see where it lives on the chip.
Memory interfaces: where the cost of every token is paidschematic, not to scale
What is proven, and what is not
What we have measured, and what comes next.
The FPGA proves the design works. The power and cost advantage is projected until the chip exists.
Proven
measured- Qwen 27B end to end on our FPGA architecture, all 64 layers
- Bit-exact: every output matches our 4-bit reference bit for bit, so it can be audited
- 4.2× faster in eight days: 533 to 126 ms of hardware time per token on the same FPGA, each step bit-exact
- Live answers from the hardware on this page
- Three model families, one bitstream: Llama 3.1 8B, OLMoE and Qwen 27B, bit-exact, no hardware changes
- Real text generation: Llama 3.1 8B at 16 words per second and OLMoE at 41, end to end
- Physically buildable: core blocks laid out at speed on an open 7 nm kit
Next
in progress- Design partner #1: Goodman Technologies signed a letter of support to evaluate VECTRA on its Puller counter-UAS vehicle, which already runs our autonomy software
- Faster responses on the next FPGA builds
- Full chip layout of the processor core
- A processor core in silicon
The product
A capable model in 16 W, beside the computer you have.
A 27B model on one accelerator module, projected for a 12 nm-class chip. Mixture-of-experts models, which read only part of their weights per word, run faster; larger models span several chips projected.
One agent
12 tokens/s at 16 W
About 1.3 J per token. Recalibrated on 31 October against the FPGA's measured per-token time projected.
Eight agents
~45 tokens/s total
Several agents share each pass through the model, at the same power. Short conversations projected.
Jetson baseline
4.2 J per token
A Jetson AGX Orin 64 GB on the same model: 5.9 tokens/s at 25 W in its 50 W mode measured.
Formats
PCIe · module · 3U VPX
PCIe for evaluation, a compact module beside Jetson or x86, 3U VPX for defense planned.
L40S measured by us with llama.cpp at 4-bit. VECTRA figures are projections from our chip model; memory sets most of the power and cost.
Path to silicon
From FPGA to a chip in partners' hands.
Pilots on the FPGA first, then our own silicon. Process and timing are plans, not commitments.
Now
FPGA pilots with design partners
Partners run their own models on the FPGA prototype, with faster responses and longer context measured against their workloads.
Next
Silicon team
An ASIC physical-design lead and a verification lead first, with a design-services partner for the backend.
Then
Core tile in silicon
A small core on a multi-project shuttle proves clock, power and function.
Then
First full chip
Core plus LPDDR5X memory interfaces, at 12 to 16 nm per our study.
Then
Boards with partners
Design partners' systems from the first silicon onward.
Why we can build it
A systems engineer's company.
The architecture, the RTL, the compiler, the runtime and the server were built by the founder, and every build, failure and measurement on the way is logged and dated.
Jack Al-Kahwati
Founder · architect
From aerospace systems to AI silicon.
Jack has spent his career on complex aerospace and defense systems, including work on Boeing aircraft and Sikorsky helicopters, and on the software and hardware around them. He founded StarDrive Inc., where Valley Semiconductor began as an internal program.
He designed VECTRA and brought it from a numerics specification to large language models from different families answering questions from FPGA hardware.
First hiresASIC physical-design lead and verification lead
Backend partnerDesign services for physical design, DFT and signoff
CustomersDesign partners with real power and cost targets
RecordA dated log of every build, shared with investors and partners under NDA
Work with us
Help us take it to silicon.
Investors: the full case, milestones and capital plan. Product teams: become a design partner and shape the first part.